1. Field of the Invention
The present invention relates to an improvement in transient characteristics in a voltage regulator.
2. Description of the Related Art
FIG. 5 illustrates a circuit diagram of a related-art voltage regulator. The related-art voltage regulator includes an error amplifier 110, PMOS transistors 120 and 201, an NMOS transistor 202, resistors 211, 212, 213, and 214, capacitors 231 and 232, a power supply terminal 100, a ground terminal 101, a reference voltage terminal 102, and an output terminal 103.
The error amplifier 110 controls a gate of the PMOS transistor 120, and an output voltage Vout is thereby output from the output terminal 103. The output voltage Vout has a value determined by dividing a voltage of the reference voltage terminal 102 by a total resistance value of the resistor 212 and the resistor 213 and multiplying the resultant value by a total resistance value of the resistor 211, the resistor 212, and the resistor 213. In order to reduce an overshoot of the output voltage Vout, the PMOS transistor 201, the NMOS transistor 202, and the resistor 214 are provided.
When an overshoot occurs in the output voltage Vout, the NMOS transistor 202 is turned on to cause a current to flow through the resistor 214. Then, a voltage is generated across the resistor 214 to turn on the PMOS transistor 201. When the PMOS transistor 201 is turned on, the gate of the PMOS transistor 120 is pulled up to a power supply voltage to turn off the PMOS transistor 120. Therefore, an overshoot in the output voltage Vout can be prevented (see, for example, FIG. 5 of Japanese Patent Application Laid-open No. 2005-92693).
In the related-art voltage regulator, however, there is a problem in that the overshoot cannot be prevented in a wide temperature range. Further, there is another problem in that a delay may occur in the detection of the overshoot and hence the overshoot may be large during the delay. In addition, in the case where a load current frequently fluctuates, there is another problem in that a circuit for preventing the overshoot or undershoot frequently operates to increase current consumption.
The related-art voltage regulator circuit with a reduced overshoot voltage is configured to detect the generation of a predetermined overshoot voltage or higher by the fact that a voltage obtained by dividing the output voltage Vout by the resistors has become equal to or higher than a threshold voltage of the NMOS transistor, and to turn off the output transistor so that the predetermined overshoot voltage or higher is not generated. Further, although not illustrated, a related-art voltage regulator circuit with a reduced undershoot voltage is configured to detect the generation of a predetermined undershoot voltage or higher by the fact that the voltage obtained by dividing the output voltage Vout by the resistors has become lower than the threshold voltage of the NMOS transistor, and to completely turn on the output transistor so that the predetermined undershoot voltage or higher is not generated.
A voltage value of the overshoot or undershoot detected by the related-art voltage regulator circuit is a value determined by multiplying the threshold of the NMOS transistor 202 by a voltage division ratio. However, the threshold of the NMOS transistor 202 decreases at high temperature and increases at low temperature. Thus, when design is made in consideration of this temperature-related variation, the overshoot voltage is significantly large at low temperature and the undershoot voltage is significantly large at high temperature. Thus, in the case where the operation is required in a wide temperature range, the overshoot voltage or the undershoot voltage to be detected cannot be decreased. Thus, there is a problem in that the rise in overshoot cannot be prevented depending on the operating temperature range, and the overshoot cannot be prevented in a wide temperature range.
Further, this problem becomes more serious as the output voltage Vout becomes higher because the voltage division ratio is large. In addition, a voltage variation in output voltage Vout is transmitted to a gate of the NMOS transistor via the voltage dividing resistors, and hence a delay occurs to delay the detection of the overshoot or undershoot voltage. Thus, there is a problem in that a delay may occur in the detection of the overshoot and the overshoot may be large during the delay.
In the case where the voltage fluctuation in output voltage Vout is transmitted to the gate of the NMOS transistor via a coupling capacitor in order to eliminate the delay described above, the variation in output voltage Vout is directly transmitted to the gate of the NMOS transistor, and the overshoot voltage or the undershoot voltage is decreased. Thus, when the load current frequently fluctuates, the circuit for preventing the overshoot or undershoot frequently operates to increase the current consumption. Thus, in the case where the load current frequently fluctuates, there is a problem in that the circuit for preventing the overshoot or undershoot frequently operates to increase the current consumption.